1. Definition
In the present application, “group III-V semiconductor” refers to a compound semiconductor that includes at least one group III element and at least one group V element, such as, but not limited to, gallium nitride (GaN), gallium arsenide (GaAs), indium aluminum gallium nitride (InAlGaN), indium gallium nitride (InGaN) and the like. Analogously, “III-nitride semiconductor” refers to a compound semiconductor that includes nitrogen and at least one group III element, such as, but not limited to, GaN, AlGaN, InN, AlN, InGaN, InAlGaN and the like.
2. Field of the Invention
The present invention is generally in the field of semiconductors. More specifically, the present invention is in the field of semiconductor packaging.
3. Background Art
Semiconductor device fabrication has consistently moved in the direction of smaller dimensions, more densely spaced layouts, and faster device operation, and that trend promises to continue. One obstacle to the achievement of optimum design efficiency has been the need to accommodate passive devices, such as resistors, and/or capacitors, and/or inductors, as accompaniments to the active semiconductor devices in a particular circuit.
Unfortunately, the conventional approach to implementing passive devices in integrated circuits typically consumes valuable space, increases component count, and introduces undesirable parasitics. For example, when implemented on-chip, the die space occupied by passives reduces the space available for active devices, or causes package size to increase undesirably. Even when implemented off-chip, passives may occupy circuit board space that could otherwise be more efficiently utilized. Moreover, the additional parasitics introduced by the traces needed to electrically connect off-chip passives to the active devices on-chip can negatively effect circuit performance. Also, increased component count, due to adding passives as separate components off-chip, increases cost and reduces manufacturing throughput.
Thus, there is a need to overcome the drawbacks and deficiencies in the art by providing a solution enabling integration of one or more passive devices utilized in combination with an active semiconductor device.